Current drive circuit and image display device

ABSTRACT

The present invention provide a display panel including a current-driven displaying elements arrayed therein, and a display device, which suppress the deterioration in the representation accuracy of grayscale levels of pixels, resulting from the variation in transistors formed within the display panel. A display panel according to the present invention is composed of a current-driven display element, a constant current control line, a constant current line, a current hold circuit, a switch circuit connected between said current-driven display element and said current hold circuit, a data line transmitting a data signal having a waveform corresponding to a grayscale level, and a control circuit provided with said data signal. Said current hold circuit outputs, when said constant current control line is deactivated, a drive current having an intensity substantially identical to that of a constant current provided thereto through said constant current line in the case that said constant current control line is activated. Said control circuit turns on and off said switch circuit in response to said data signal.

TECHNICAL FIELD

The present invention is related to current drive circuits and imagedisplay devices, and more particularly, to display panels and imagedisplay devices, including current-driven display elements and currentdrive circuits for driving the same.

BACKGROUND ART

The organic EL display, composed of an array of organicelectro-luminescence elements (organic EL elements), is one of thepromising display devices from various advantages. Organic EL displayscan be operated on reduced direct current voltages, and achieves highefficiency, namely, high brightness. Moreover, organic EL displaysexhibit higher response speed than liquid crystal displays, and improvedtemperature characteristics at low temperatures. Additionally, organicEL displays achieve improved visibility through self light emitting, andtherefore do not require backlights, differently from liquid crystaldisplays. The fact that no backlight is required preferably makesdisplays thinner.

Among passive and active matrix methods, which are known as drivingmethods of organic EL displays, the active matrix method is a promisingdriving method of organic EL displays. The active matrix methoddesignates a method that involves providing TFTs (Thin Film Transistor)on display panels to activate organic EL elements. The active matrixmethod, which exhibits excellent light emission efficiency, is expectedto achieve high image quality. Additionally, the active matrix methodachieves extension of display lifetime through reduction in drivecurrents of organic EL elements,

Japanese Laid Open Patent Application (JP-A-Heisei, 11-282410) disclosesa driving circuit of organic EL elements for an active matrix method.FIG. 1 is a circuit diagram of the disclosed driving circuit. Thedriving circuit is composed of n-channel transistors 131, 132, acapacitor element 133, and switches 134, 135. TFTs are used as then-channel transistors 131, 132. The n-channel transistors 131, and 132form a current mirror. This current mirror is supplied with a signalcurrent corresponding to the brightness of an organic EL element 103from a signal line 104. The current mirror generates a drive current fordriving the organic EL element 103 in response to the supplied signalcurrent.

One problem of this driving circuit is that the generated drive currentmay not correspond to the signal current due to the non-uniformity ofthe properties of the n-channel transistors 131, and 132. TFTs, whichare used as the n-channel transistors 131, 132, tend to exhibitincreased non-uniformity, differently from transistors integrated withina silicon single crystal; TFTs suffer from increased variance in carriermobilities, film thicknesses of gate dielectrics, and thresholdvoltages. Even for a pair of adjacent TFTs, the threshold voltagesthereof may be different by about several 10 mV. The variation in theproperties of the n-channel transistors 131, and 132 may causenon-uniformity in brightnesses of a plurality of organic EL elements103, that is, a plurality of pixels, for the same signal current to besupplied thereto. This undesirably deteriorates the image quality of thedisplay panel.

Another problem of the driving circuit is that the drive currentsupplied to the organic EL element 103 may be nonlinear with respect tothe signal current, because of a parasitic capacitance 136 of the signalline 104. A part of the signal current is used to charge the parasiticcapacitance 136 of the signal line 104, and not supplied to the currentmirror. The part of the signal current used to charge the parasiticcapacitance 136 does not contribute to the driving current. For a minutesignal current, in particular, the part exhausted to charge theparasitic capacitance 136 cannot be ignored. As a result, as shown inFIG. 2, the drive current I_(out) exhibits nonlinearity with respect toa signal current I_(in). The nonlinearity of the drive current I_(out)prevents a low grayscale level from being accurately represented, anddegrades the image quality of the display panel.

The influence of the nonlinearity of the drive current I_(out) isimportant to the active matrix method in which the signal current isrelatively small. In the active matrix method, the drive currentsupplied to the organic EL elements ranges between 1/50 and 1/100 of thedrive current of the passive matrix method; the minimum drive currentranges between several nA and ten-odd nA. The small drive current maycause a trouble that the charging of the parasitic capacitance 136 isnot completed in one frame, which disables the pixels to represent thelow brightness.

Japanese Laid Open Patent Application (JP-A-Heisei, 5-35202) discloses adrive circuit adapted to the active matrix method, in order to suppressthe influence caused by the variation in properties of elements.Nevertheless, the drive circuit is adapted to drive a voltage-drivenliquid crystal; the drive circuit does not solve the above-mentionedproblems.

DISCLOSURE OF INVENTION

Therefore, an object of the present invention is to provide a displaypanel including a current-driven displaying elements arrayed therein anda display device, which suppress the deterioration in the representationaccuracy of grayscale levels of pixels, resulting from the variation intransistors formed within the display panel.

Another object of the present invention is to provide a display panelincluding a current-driven displaying elements arrayed therein and adisplay device, which suppress the deterioration in the representationaccuracy of grayscale levels of the pixels, resulting from parasiticcapacitances of signal lines formed within the display panel.

A display panel according to the present invention is composed of acurrent-driven display element, a constant current control line, aconstant current line, a current hold circuit, a switch circuitconnected between said current-driven display element and said currenthold circuit, a data line transmitting a data signal having a waveformcorresponding to a grayscale level, and a control circuit provided withsaid data signal. Said current hold circuit outputs, when said constantcurrent control line is deactivated, a drive current having an intensitysubstantially identical to that of a constant current provided theretothrough said constant current line in the case that said constantcurrent control line is activated. Said control circuit turns on and offsaid switch circuit in response to said data signal. Said current-drivendisplay element is typically an organic EL element.

The structure of this display panel is effective for eliminating theinfluence of the variance in the properties of transistors formedthereon, and effectively improving the image quality of the displaydevice. The display panel is driven by providing the current-drivendisplay element with a drive current having an intensity identical tothat of the constant current. The grayscale level of the current-drivendisplay element is controlled by a waveform of the data signal, that is,the duration while the drive current is provided for the current-drivendisplay element. The display panel such constructed allows the constantcurrent developed through the constant current line to be increased tosuch a degree that a current necessary for charging a parasiticcapacitor is negligible. Therefore, the display panel in this embodimenteasily eliminates the influence of the parasitic capacitor of theconstant current line.

Such structure is especially effective in the case that all of thetransistors contained within said current hold circuit, said switchcircuit, and said control circuit are TFTs.

When the display panel additionally includes additional switch circuitconnected between said constant current line and said current holdcircuit, and said current hold circuit is connected to a power supplyterminal, it would be preferable that said additional switch circuitelectrically connects said constant current line with said current holdcircuit, and thereby allows said constant current to flow from saidpower supply terminal to said constant current line through said currenthold circuit.

all MOS transistors contained within said current hold circuit, saidswitch circuit, said additional switch circuit, and said control circuitpreferably have the same conductivity type.

When said additional switch circuit includes a first MOS transistor, afirst source/drain of said first MOS transistor is connected to saidconstant current line, a second source/drain of said first MOStransistor is connected to said current hold circuit, and a gate of saidfirst MOS transistor is connected to said constant current control line.

When said current hold circuit includes a drive MOS transistor, a firstcapacitor element, a second MOS transistor, then a source of said driveMOS transistor is connected to a power supply terminal, a drain of saiddrive MOS transistor is connected to said switch circuit and saidadditional switch circuit; said first capacitor element is connectedbetween a gate and source of said drive MOS transistor; a source and adrain of said second MOS transistor are connected to said gate and drainof said drive MOS transistor, respectively; and a gate of said secondMOS transistor is connected to said constant current control line.

It would be preferable that said constant current flows from said powersupply terminal to said constant current line through said drive MOStransistor, said additional switch circuit, and thereby said firstcapacitor element is charged to a source-to-gate voltage of said driveMOS transistor, and said constant current is supplied for said currenthold circuit multiple times for one frame period.

For example, said constant current is preferably supplied for saidcurrent hold circuit every time said data signal is provided for saidcontrol circuit.

When said current hold circuit additionally includes a third MOStransistor, said third MOS transistor has a first source/drain connectedto said drain of said drive MOS transistor, a first source/drain of saidthird MOS transistor is connected to said switch circuit, and said thirdMOS transistor has a gate connected to said constant current controlline.

Moreover, when the display panel further includes a sub constant currentcontrol line having a potential complementary to a potential on saidconstant current control line, and said current hold circuitadditionally includes a third MOS transistor, it would be preferablethat said third MOS transistor has a first source/drain connected tosaid drain of said drive MOS transistor, a second source/drain connectedto said switch circuit, and a gate connected to said sub constantcurrent control line, and conductivity types of said first MOStransistor, said second MOS transistor, and said third MOS transistorare same. Such structure is effective for allowing MOS transistorsformed on the display panel to have the same conductivity type.

When the display panel further includes a data-line control lineconnected to said control circuit, it is preferable that said controlcircuit is composed of a potential hold circuit outputting a potentialsubstantially identical to a potential of said data signal from a signaloutput when said data line control line is activated, and holding apotential on said signal output when said data line control line isdeactivated, and that said switch circuit is turned on and off, inresponse to said potential on said signal output of said potential holdcircuit.

When said switch circuit includes a fourth MOS transistor and saidpotential hold circuit is composed of a fifth MOS transistor, and asecond capacitor element, a first source/drain of said fourth MOStransistor is connected to said current hold circuit, a secondsource/drain of said fourth MOS transistor is connected to saidcurrent-driven display element, a first source/drain of said fifth MOStransistor is connected to said data line, a second source/drain of saidfifth MOS transistor is connected to said signal output, and a gate ofsaid fifth MOS transistor is connected to said data-line control line,and said second capacitor element is connected between a power supplyterminal and said signal output.

It would be effective for eliminating the influence of the parasiticcapacitance of the constant current line that the display panel furtherincludes a dummy circuit connected to said constant current line, andsaid dummy circuit is provided with said constant current through saidconstant current line during an inactive period while said constantcurrent control line is deactivated.

In detail, it would be preferable that the display panel additionallyincludes a dummy constant current control line which is activated duringan inactive period while said constant current control line isdeactivated, that said dummy current includes a drive transistor, afirst MOS transistor, and a second MOS transistor, said first MOStransistor having a first source/drain connected to said constantcurrent line, and a gate connected to said dummy constant currentcontrol line, said drive MOS transistor having a source connected to apower supply terminal, and a drain connected to a second/source drain ofsaid first MOS transistor, and said second MOS transistor having asource and a drain connected to a gate and said drain connected to saiddrive MOS transistor, respectively, and a gate connected to said dummyconstant current control line.

It would be more preferable that said dummy pixel is provided with saidconstant current through said constant current line not during the wholeof an inactive period while said constant current control line isdeactivated, but during a predetermined period out of the inactiveperiod immediately before said constant current control line isactivated. It would be further preferable that said predetermined periodis longer than a time constant of charging a parasitic capacitor of saidconstant current line.

A driving method according to the present invention is a method ofdriving a display panel including a current-driven display element, adrive MOS transistor, a capacitor element connected between a gate and asource of said drive MOS transistor, a first switch connected between adrain and said gate of said drive MOS transistor, and a second switchconnected between said drain of said drive MOS transistor and thecurrent-driven display element. The driving method is composed of:

a first step of developing a constant current through said drive MOStransistor with said first switch turned on and with said second switchturned off,

a second step of providing a drive current for said current-drivendisplay element with said first switch turned off and with said secondswitch turned on.

The driving method is especially useful for the case when said displaypanel further includes a constant current line, and said constantcurrent is provided for said drive MOS transistor through said constantcurrent line.

Said first step is preferably performed multiple times for one frameperiod.

The present invention suppresses the deterioration in the representationaccuracy of grayscale levels of pixels, resulting from the variation intransistors formed within the display panel.

In another aspect, the present invention suppresses the deterioration inthe representation accuracy of grayscale levels of the pixels, resultingfrom parasitic capacitances of signal lines formed within the displaypanel.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram illustrating a structure of a drivingcircuit of a conventional organic EL element;

FIG. 2 is a graph showing an input/output property of the drivingcircuit of the conventional organic EL element;

FIG. 3 is a circuit diagram illustrating a structure of a display devicein a first embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating a structure of a pixel of thedisplay device in the first embodiment;

FIG. 5 shows the detailed structure of the pixel;

FIG. 6 is a timing chart illustrating operations of the display devicein the first embodiment;

FIG. 7 is a timing chart illustrating a method of controlling thegrayscale level of the pixel;

FIG. 8 is a graph illustrating a relation between a conduction timeduring which a drive current flows through an organic EL element and thegrayscale level of the pixel;

FIG. 9 is a table showing a correspondence between the conduction timeand the grayscale level of the pixel;

FIG. 10 is a circuit diagram partially illustrating the structure of thedisplay device in the first embodiment in the present invention;

FIG. 11 is a graph showing a change in a potential of a constant currentcontained in the display device in the first embodiment of the presentinvention;

FIG. 12 is a circuit diagram illustrating a structure of a displaydevice in the second embodiment of the present invention;

FIG. 13 is a circuit diagram of a dummy circuit contained in the displaydevice in the second embodiment of the present invention;

FIG. 14 is a timing chart illustrating operations of the display devicein the second embodiment;

FIG. 15 is a timing chart illustrating operations of a display device ina third embodiment;

FIG. 16 is a timing chart illustrating operations of a display device ina fourth embodiment;

FIG. 17 is a circuit diagram illustrating a structure of a pixelcontained in a display device in a fifth embodiment;

FIG. 18 is a timing chart illustrating operations of the display devicein the fifth embodiment;

FIG. 19 is a circuit diagram illustrating a structure of a pixelcontained in a display device in a sixth embodiment;

FIG. 20 is a timing chart illustrating operations of the display devicein the sixth embodiment;

FIG. 21 is a circuit diagram illustrating a structure of a pixelcontained in a display device of a seventh embodiment;

FIG. 22 is a timing chart illustrating operations of the display devicein the seventh embodiment;

FIG. 23 is a circuit diagram illustrating a structure of a displaydevice in an eighth embodiment;

FIG. 24 is a circuit diagram illustrating a structure of a pixelcontained in the display device in the eighth embodiment;

FIG. 25 is a circuit diagram illustrating the detailed structure of thepixel contained in the display device in the eighth embodiment;

FIG. 26 is a timing chart illustrating operations of the display devicein the eighth embodiment; and

FIG. 27 is a timing chart illustrating operations of a display device ina ninth embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

The preferable embodiment of the present invention will be describedbelow with reference to the attached drawings.

First Embodiment

FIG. 3 shows a display device in a first embodiment of the presentinvention. The display device is provided with a display panel 50. Thedisplay panel 50 is composed of N constant current lines 4, M constantcurrent control lines 5, N data lines 6, M data-line-control lines 7,and pixels 12 arrayed in M columns and N rows. The constant currentlines 4, the constant current control lines 5, the data lines 6, thedata-line-control lines 7 and the pixels 12 may be distinguished fromeach other with a subscript, if necessary. The constant current lines 4and the data lines 6 are extended along an x-axis direction, and theconstant current control lines 5 and the data-line control lines 7 areextended along a y-axis direction. A pixel 12 _(i,j) is connected to aconstant current line 4 _(j), a constant current control line 5 _(i), adata line 6 _(j), and a data-line control line 7 _(i). The constantcurrent control lines 5 are low active, while the data lines 6 and thedata-line control lines 7 are high active.

The constant current lines 4 are connected to a constant current supplycircuit 13. The constant current control lines 5 are connected to aconstant current control line drive circuit 14. The constant currentcontrol line drive circuit 14 scans and sequentially activates theconstant current control lines 5. The constant current supply circuit 13supplies the pixels 12 connected to the activated constant currentcontrol lines 5 with constant currents of a predetermined intensity inparallel, through the constant current lines 4.

The data lines 6 are connected to a data signal generating circuit 15,and the data-line control lines 7 are connected to a data-line controlline drive circuit 16. The data-line control line drive circuit 16 scansand sequentially activates the data-line control lines 7. The datasignal generating circuit 15 provides the pixels 12 connected to theactivated constant current control lines 5 with data signals in parallelthrough the data lines 6. As described later, the data signals havewaveforms corresponding to the grayscale levels of the pixels 12. Whendata signals are activated, each pixel 12 emits light in response to theactivated data signals. The grayscale levels of the pixels 12 arecontrolled through time division drive.

FIG. 4 is a block diagram illustrating the structure of the pixel 12.The pixel 12 is each composed of a power supply terminal 1, a groundterminal 2, an organic EL element 3, a switch 8, a current hold circuit9, a potential hold circuit 10 and a switch 11. The current hold circuit9, the switch 11, and the organic EL element 3 are connected in seriesbetween the power supply terminal 1 and the ground terminal 2. A currentinput 9 a of the current hold circuit 9 is connected to the constantcurrent line 4 through the switch 8. A control input 8 a of the switch 8and a control input 9 b of the current hold circuit 9 are connected tothe constant current control line 5. A control input 11 a of the switch11 is connected to a signal output 10 a of the potential hold circuit10. A signal input 10 b of the potential hold circuit 10 is connected tothe data line 6, and a control input 10 c of the potential hold circuit10 is connected to the data-line control line 7. The current holdcircuit 9 is configured to, while the constant current control line 5 isdeactivated, output a drive current having an intensity substantiallyequal to that of the constant current supplied thereto in the case thatthe constant current control line 5 is activated, from a current output9 c. The potential hold circuit 10 functions as a control circuit forcontrolling the turn-on and turn-off of the switch 11. The potentialhold circuit 10 is configured to develop on the signal output 10 a apotential substantially equal to the potential of the data signalgenerated on the data line 6 while the data-line control line 7 isactivated, and to hold the potential of the signal output 10 a while thedata-line control line 7 is deactivated.

FIG. 5 shows a typical configuration of the switch 8, the current holdcircuit 9, the potential hold circuit 10, and the switch 11. The switch8 is composed of a p-channel MOS transistor 21. The p-channel MOStransistor 21 has a source connected to the constant current line 4, agate connected to the constant current control line 5, and a drainconnected to the current input 9 a of the current hold circuit 9.

The current hold circuit 9 includes p-channel MOS transistors 22, 23, acapacitor element 24 and an N-channel MOS transistor 25. A source and adrain of the P-channel MOS transistor 22 are connected to a gate and adrain of the P-channel MOS transistor 23, respectively. A gate of theP-channel MOS transistor 22 is connected to the constant current controlline 5. The P-channel MOS transistor 23 has a source connected to thepower supply terminal 1, and a drain connected to a drain of theN-channel MOS transistor 25 and to the current input 9 a. The capacitorelement 24 is connected between the source and the gate of the P-channelMOS transistor 23. The N-channel MOS transistor 25 has a gate connectedto the constant current control line 5, and a source connected to thecurrent output 9 c.

As described later, the intensity of the drive current supplied to theorganic EL element 3 is dependent on the voltage between the source andgate of the P-channel MOS transistor 23. Therefore, the P-channel MOStransistor may be referred to as the drive transistor 23, hereinafter.

The potential hold circuit 10 includes an N-channel MOS transistor 26and a capacitor element 27. The N-channel MOS transistor 26 has a drainconnected to the data line 6, and a gate connected to the data-linecontrol line 7. A source of the N-channel MOS transistor 26 is connectedto the signal output 10 a. The capacitor element 27 is connected betweenthe source of the N-channel MOS transistor 26 and the power supplyterminal 1.

The switch 11 includes an N-channel MOS transistor 28. The N-channel MOStransistor 28 has a drain connected to the current output 9 c of thecurrent hold circuit 9, and a source connected to the organic EL element3. A gate of the N-channel MOS transistor 28 is connected to the signaloutput 10 a of the potential hold circuit 10.

All of the above-mentioned P-channel MOS transistors 21 to 23 andN-channel MOS transistors 25, 26 and 28 are formed with TFTs.

FIG. 6 is a timing chart showing operations of a certain pixel 12. Thecurrent hold circuit 9 is programmed with the constant current I₄ whenthe constant current control line 5, which is low active, is activated.In other words, in response to a potential V₅ of the constant currentcontrol line 5 being pulled down to the low level, the capacitor element24 is charged to a voltage substantially equal to the source-to-gatevoltage necessary for the drive MOS transistor 23 to develop theconstant current I₄.

Programming the current hold circuit 9 with the constant current I₄ isachieved as follows. In response to the activation of the constantcurrent control line 5, the switch 8 (that is, the P-channel MOStransistor 21) is turned on, and thereby the current hold circuit 9 isconnected to the constant current line 4. Additionally, the P-channelMOS transistor 22 is turned on to thereby allow the drive MOS transistor23 to be diode-connected. The N-channel MOS transistor 25 is turned off,and the drive MOS transistor 23 is electrically isolated from theorganic EL element 3. Moreover, the constant current supply circuit 13develops the constant current I₄ from the power supply terminal 1 to theconstant current line 4 through the drive MOS transistor 23 and theswitch 8. Forcedly developing the constant current I₄ through the driveMOS transistor 23 by the constant current supply circuit 13 achievesadjustment of the source-to-gate voltage of the drive MOS transistor 23so that the drive MOS transistor 23 develops the constant current I₄therethrough. This results in that the capacitor element 24 is chargedto a voltage substantially equal to the source-to-gate voltage necessaryfor the drive MOS transistor 23 to develop the constant current I₄therethrough.

Moreover, the intensity of the constant current I₄ is selected to belarge enough to ignore the current required to charge the parasiticcapacitance of the constant current line 4. In other words, the durationwhile the constant current I₄ flows is selected to be sufficientlylarger than a time constant of charging the parasitic capacitance of theconstant current line 4. This eliminates the influence of the parasiticcapacitance of the constant current line 4.

The duration while the constant current I₄ flows is set to besufficiently larger than a time constant of charging the capacitorelement 24. This is important for charging the capacitor element 24 tothe source to gate voltage necessary for the drive MOS transistor 23 todevelop the constant current I₄, regardless of the properties of theTFTs constituting the pixel 12.

In response to the deactivation of the constant current line 5, thecurrent hold circuit 9 is then placed into a “Hold State”, that is, astate in which the drive current I₉ substantially equal to the constantcurrent I₄ is outputable from the current output 9 c. In response to theconstant current line 5 being deactivated, namely, pulled up to the highlevel, the switch 8 (that is, the P-channel MOS transistor 21) is turnedoff, and the current hold circuit 9 is disconnected from the constantcurrent line 4. Additionally, the P-channel MOS transistor 22 is turnedoff, and the capacitor element 24 holds the source-to-gate voltagenecessary for the drive MOS transistor 23 to develop the constantcurrent I₄. This results in that the source-to-gate voltage of the driveMOS transistor 23 is maintained at such a voltage that the drive MOStransistor 23 outputs the drive current I₉ equal to the constant currentI₄. Moreover, the N-channel MOS transistor 25 is turned on, and thedrive MOS transistor 23 is connected to the current output 9 c. Thisallows the current hold circuit 9 to be placed into the state in whichthe drive current I₉ substantially equal to the constant current I₄ isoutputable from the current output 9 c.

Simultaneously with the deactivation of the constant current line 5, thedata-line control line 7 is activated, namely, a potential V₇ of thedata-line control line 7 is pulled up to the high level.

In response to the data-line control line 7 being activated, thepotential hold circuit 10 is programmed with the data signal through thedata line 6. In other words, the potential on the signal output 10 a ofthe potential hold circuit 10 is driven to the potential of the datasignal, and the capacitor element 27 is charged to the potentialdifference between the data signal and the power supply terminal 1. Whenthe data signal is active, namely, if the data signal is set to the highlevel, the switch 11 (namely, the NMOS transistor 28) is turned on, andthe current hold circuit 9 is connected to the organic EL element 3. Thecurrent hold circuit 9 supplies the drive current I₉, which is equal tothe constant current I₄ to the organic EL element 3, and the organic ELelement 3 emits the light. When the data signal is deactivated, theswitch 11 (namely, the NMOS transistor 28) is turned off, and theorganic EL element 3 does not emit light.

The data-line control line 7 is then deactivated. Even after thedeactivation of the data-line control line 7, the potential on thesignal output 10 a of the potential hold circuit 10 is maintained at thepotential of the data signal inputted to the potential hold circuit 10,due to the operation of the capacitor element 27. In response to thepotential of the signal output 10 a, the organic EL element 3 is keptemitting light or not emitting light. The potential on the signal output10 a of the potential hold circuit 10 is maintained until the datasignal is newly inputted to the potential hold circuit 10 after thedata-line control line 7 is next activated.

In order to achieve a desired grayscale level on the pixel 12, theorganic EL element 3 is time-divisionally driven. The intensity of thedrive current I₉ supplied to the organic EL element 3 is kept constantwhile the organic EL element 3 emits light; the grayscale level of thepixel 12 is not adjusted with the intensity of the drive current I₉.

FIG. 7 is a timing chart showing the driving method of the organic ELelement 3 for achieving the desired grayscale level on the organic ELelement 3. One frame period is composed of a constant current writeperiod, and a constant current hold period following it. Programming thecurrent hold circuit 9 with the constant current I₄ is executed duringthe constant current write period; the drive current is not supplied forthe organic EL element 3 during the constant current write period. Thatis, the constant current write period is the blanking period while thepixel 12 is not turned on.

The constant current hold period is divided into n periods T₁ to T_(n)having lengths of t₁ to t_(n), respectively. The t₁ to t_(n) satisfy thefollowing relation:t _(i)=2⁻¹ t ₁  (1)where i is an integer between 1 and n. In this embodiment, n is 4.

The periods T₁ through T_(n) are each composed of a write period and ahold period. During the write period, the data signal is provided to thepotential hold circuit 10 through the data line 6. Additionally, thedata-line control line 7 is activated, and the potential hold circuit 10is programmed with the potential of the data signal. During the holdperiod, the data-line control line 7 is deactivated, and the writtenpotential of the data signal is held on the signal output 10 a of thepotential hold circuit 10. When the activated data signal is inputted tothe potential hold circuit 10 during the write period of a certainlightening period T_(i), the drive current I₉ is supplied to the organicEL element 3 over the whole of the lightening period T_(i) (namely, bothof the write period and the hold period). When the deactivated datasignal is inputted to the potential hold circuit 10, on the other hand,the drive current I₉ is not supplied to the organic EL element 3 duringthe period T_(i).

The brightness of the pixel 12 is adjusted the length of the periodwhile the organic EL element 3 is turned on. The data signal isgenerated so as to indicate during which period(s) the organic ELelement 3 is turned on, out of the periods T₁ to T_(n). In order to turnon the organic EL element 3 during the period T_(i), the data signal isactivated during the write period within the period T_(i). In order toturn off the organic EL element 3 during the period T_(j), the datasignal is deactivated during the write period of the period T_(j). Inorder to increase the brightness of the pixel 12, the data signal isgenerated and supplied to the potential hold circuit 10, so that thedata signal has a waveform indicating that the drive current I₉ issupplied to the organic EL element 3 for a long period of time. In orderto decrease the brightness of the pixel 12, in contrast, the data signalis generated so that the data signal has a waveform indicating that thedrive current I₉ is supplied to the organic EL element 3 only for ashort period of time.

Such operation enables the display device in this embodiment torepresent 2 ^(n) grayscale levels. FIG. 8 is a graph showing the lengthof the supply time during which the drive current I₉ is supplied to theorganic EL element 3, and the grayscale levels of the pixel 12, whileFIG. 9 is a table showing the correspondence between the grayscalelevels of a certain pixel 12 and the supply time. As shown in FIGS. 8and 9, the brightness of the pixel 12 is increased through lengtheningthe supply time during which the drive current I₉ is supplied to theorganic EL element 3, while the brightness of the pixel 12 is decreasedthrough reducing the supply time.

The display panel in this embodiment eliminates the influence of thevariation in the properties of TFTs, and effectively improves the imagequality of the display device. Due to the configuration of the pixel 12as mentioned above, the drive current I₉ supplied to the organic ELelement 3 is substantially coincident with the constant current I₄supplied to the pixel 12 from the constant current supply circuit 13. Asmentioned above, programming the current hold circuit 9 with theconstant current I₄ achieves charging the capacitor element 24 of thepixel 12 to the voltage necessary for the drive transistor 23 to drivethe current substantially equal to the constant current I₄. While thedrive current I₉ is supplied to the organic EL element 3, thesource-to-gate voltage of the drive transistor 23 is maintained by thecapacitor element 24 so that the drive current I₉ substantially equal tothe constant current I₄ is outputted to the drive transistor 23.Therefore, the intensity of the drive current I₉ does not depend on theproperties of the drive transistor 23 composed of TFTs; the intensity ofthe drive current I₉ is substantially equal to that of the constantcurrent I₄. The brightness of the pixel 12 does not suffer from theinfluence of the variation in the properties of the drive transistor 23.Accordingly, the display panel in this embodiment effectively improvesthe image quality of the display device.

Additionally, the display panel in this embodiment eliminates theinfluence of the parasitic capacitance of the constant current line 4,and thereby achieves the desired grayscale level on the pixel 12. In thedisplay panel in this embodiment, the constant current I₄ developedthrough the constant current line 4 is increased to such a degree thatthe current required charging the parasitic capacitance of the constantcurrent line 4 can be ignored. Accordingly, the display panel in thisembodiment easily eliminates the influence of the parasitic capacitanceof the constant current line 4.

Second Embodiment

FIG. 10 is a diagram partially showing the display panel 50. FIG. 10illustrates the pixels 12 _(1, k) to 12 _(M, k) on the k–th row of thedisplay panel 50. The constant current lines 4, which intersect theconstant current control lines 5, the data-line control lines 7, thepower supply line and the ground line (not shown in FIG. 10), have aparasitic capacitance 29. The parasitic capacitance 29 is charged whilethe constant currents I₄ flow through the constant current lines 4, anddischarged while the supply of the constant current I₄ is stopped.

FIG. 11 is a graph showing the change in a potential V_(4 k) on theconstant current line 4 _(k) during one frame period. In the constantcurrent write period, the constant currents I₄ are sequentially writtenonto the current hold circuits 9 of the pixels 12, column by column. Theparasitic capacitance 29 is started to be discharged immediately afterthe completion of the writing of the constant current I₄ to the currenthold circuits 9 of the pixels 12, for all the columns, and the potentialV_(4 k) on the constant current line 4 _(k) begins to be dropped.

As described in the first embodiment, sufficiently increasing theconstant current I₄ flowing through the constant current line 4eliminates the influence of the parasitic capacitance 29 on theprogramming of the current hold circuit 9 with the constant current;even when the parasitic capacitance 29 is discharged and thereby thepotential on the constant current line 4 is decreased, there is noinfluence on the writing to the current hold circuit 9 of the constantcurrent I₄ if the constant current I₄ is made sufficiently large.

In some cases, however, the organic EL elements 3 may not require theincrease in the constant current I₄ flowing through the constant currentline 4, namely, the drive current I₉, due to the properties thereof. Forthe architecture in which the constant current I₄ flowing through theconstant current line 4 is not sufficiently increased, a considerabledifference is induced between the constant current flowing into theconstant current line 4 and the constant current supplied to the currenthold circuit 9, because a part of the constant current I₄ is used tocharge the parasitic capacitance 29. This involves that the constantcurrent I₄ cannot be accurately written onto the current hold circuit 9.

In a second embodiment, in order to solve such problem, dummy pixels 12_(M+1, 1) to 12 _(M+1, N) (one shown) and a dummy constant currentcontrol line 5 _(M+1) are additionally disposed within the display panel50, as shown in FIG. 2. The dummy constant current control line 5 _(M+1)is low active, as is the case of the constant current control line 5_(M).

FIG. 13 shows the configuration of the dummy pixel 12 _(M+1, k). Thedummy pixel 12 _(M+1, k) is composed of P-channel MOS transistors 21′ to23′, all of which are formed of TFTs. A source of the P-channel MOStransistor 23′ is connected to the power supply terminal 1, while a gateand a drain of the P-channel MOS transistor 23′ are connected to asource and a drain of the P-channel MOS transistor 22′, respectively. Agate of the P-channel MOS transistor 22′ is connected to the dummyconstant current control line 5 _(M+1). The P-channel MOS transistor 21′has a drain connected to the drains of the P-channel MOS transistor 22′and the P-channel MOS transistor 23′, and a source connected to theconstant current line 4 _(k). A gate of the P-channel MOS transistor 21′is connected to the dummy constant current control line 5 _(M+1).

FIG. 14 is a timing chart showing the operation of the display device inthis embodiment. During the constant current write period, the constantcurrent control lines 5 ₁ to 5 _(M) are sequentially activated, and theconstant currents I₄ are written onto the current hold circuits 9 of thepixels 12 for each column. It should be noted that the constant currentcontrol lines 5 ₁ to 5 _(M) are low active. The potential V₄ of theconstant current line 4 while the constant current I₄ is written to thecurrent hold circuit 9 is represented by the following equation:V ₄ =V _(CC) −V _(GS),where V_(CC) is the potential on the power supply terminal 1, and V_(GS)is the source to gate voltage of the drive transistor 23 necessary forthe drive transistor 23 to drive the drive current I₉ equal to theconstant current I₄.

At the beginning of the constant current hold period, following theconstant current write period, the dummy constant current control line 5_(M+1), which is low active, is activated; the potential V_(5M+1) of thedummy constant current control line 5 _(M+1) is pulled down to the lowlevel. In response to the pull-down of the dummy constant currentcontrol line 5 _(M+1), the P-channel MOS transistors 21′ and 22′ areturned on. The turn on of the P-channel MOS transistor 22′ allows theP-channel MOS transistor 23′ to be diode-connected. Additionally, theP-channel MOS transistor 23′ is electrically connected to the constantcurrent line 4 through turning on the P-channel MOS transistor 21′, andthis allows the constant current I₄ to flow from the power supplyterminal 1 to the constant current line 4 through the P-channel MOStransistor 23′. Continuously developing the constant current I₄ on theconstant current line 4 suppresses the discharge of the parasiticcapacitance 29. This reduces the intensity of the current required torecharge the parasitic capacitance 29, and ideally eliminates thenecessity for recharging the parasitic capacitance 29. Through theabove-described operations, the dummy pixels 12 _(M+1, 1) to 12_(M+1, N) effectively solve the problem that the current hold circuit 9is not accurately programmed with the constant current I₄ for the casewhen the constant current I₄ flowing through the constant current line 4is small.

Preferably, the properties of the P-channel MOS transistor 23′ of thedummy pixel 12 _(M+1, k) are selected to be substantially equal to thoseof the drive transistor 23 of the pixel 12. More specifically, the sizeof the P-channel MOS transistor 23 is selected to be substantially equalto that of the drive transistor 23. This allows the source-to-gatevoltages V_(GS) of the P-channel MOS transistor 23′ and the drivetransistor 23 to be substantially equal to each other, and thereby thepotential V₄ of the constant current line 4 is kept constant as shown inFIG. 14. This preferably eliminates the need for recharging theparasitic capacitance 29.

As explained above, the dummy pixels 12 _(M+1, 1) to 12 _(M+1, N)suppress the decrease in the potential V₄ on the constant current line4. Therefore, the dummy pixels 12 _(M+1, 1) to 12 _(M+1, N)reduce theintensity of the current required to charge the parasitic capacitance29, and ideally eliminate the need for charging the parasiticcapacitance 29. This is especially useful in the case when the constantcurrent I₄ flowing through the constant current line 4 is not allowed tobe increased.

Third Embodiment

In a third embodiment, operations of the display device are modified inorder to reduce the power consumption, as shown in the timing chart ofFIG. 15. In this embodiment, the dummy constant current control line 5_(M+1) is not activated immediately after the end of the constantcurrent write period (namely, immediately after the start of theconstant current hold period); the potential V_(5M+1) of the dummyconstant current control line 5 _(M+1) continues to be maintained at thehigh level. Since the dummy constant current control line 5 _(M+1) isdeactivated and the supply of the constant current I₄ is stopped, thepotential of the constant current line 4 starts to be decreased.

The dummy constant current control line 5 _(M+1) begins to be activated,a time of t_(dm) before the end of the constant current hold period(namely, the start of a next constant current write period). The dummyconstant current control line 5 _(M+1) continues to be activated untilthe end of the constant current hold period, and is deactivated when thenext constant current write period is started. The time t_(dm) duringwhich the dummy constant current control line 5 _(M+1) is activated isset to be sufficiently larger than the time constant of charging theparasitic capacitance 29 so that the potential of the constant currentline 4 reaches the potential of V_(CC)−V_(GS). This eliminates thenecessity of recharging the parasitic capacitance 29, and enables thedesirable constant current I₄ to be written to the current hold circuit9 of the pixel 12, as is the case of the second embodiment.

Additionally, the power consumption is effectively decreased in thethird embodiment, since the constant current hold period includes theperiod while the supply of the constant current I₄ is stopped.

Fourth Embodiment

In a fourth embodiment, operations of the display device is modified asshown in FIG. 16 in order to suppress the influence of discharge of thecapacitor element 24 within the current hold circuit 9; theconfiguration of the display device is equal to the first embodiment.The capacitor element 24 is discharged due to the minor leakthereacross, and this decrease the voltage across the capacitor element24 during the constant current hold period. This is not preferablebecause the difference between the constant current I₄ and the drivecurrent I₉ is increased, and thereby the accuracy in the grayscale levelof the pixel 12 is deteriorated.

In order to sustain the voltage across the capacitor element 24, in thefourth embodiment, the current hold circuit 9 is programmed with theconstant current I₄ multiple times for one frame period, as shown inFIG. 16. The constant current control line 5 is activated when the datasignal is written through the data line 6 onto the potential holdcircuit 10, namely, while the data-line control line 7 is activated, andthereby the current hold circuit 9 is programmed with the constantcurrent I₄. Repeatedly programming the current hold circuit 9 with theconstant current I₄, namely, repeatedly charging the parasiticcapacitance 29 suppresses the decrease in the voltage across thecapacitor element 24 during the constant current hold period. Thisreduces the difference between the constant current I₄ and the drivecurrent I₉, and improves the accuracy in the graylevel of the pixel 12.

Fifth Embodiment

In a fifth embodiment, as shown in FIG. 17, the channel conductivitytypes of some of TFTs contained in the pixel 12 are altered. In detail,the N-channel MOS transistor 26 within the potential hold circuit 10 isreplaced with a P-channel MOS transistor 26′, and the N-channel MOStransistor 28 constituting the switch 11 is replaced with a P-channelMOS transistor 28′. This is accompanied by that the data line 6 and thedata-line control line 7 are changed to be low active. That is, as shownin FIG. 18, the polarities of the data signal transmitted through thedata line 6 and the signal generated on the data-line control line 7 areinverted. It is apparent to those skilled in the art that the pixel 12shown in FIG. 17 is substantially equivalent to the pixel 12 shown inFIG. 12.

Sixth Embodiment

In a sixth embodiment, as shown in FIG. 19, the N-channel MOS transistor25 is removed from the pixel 12 in order to reduce the number of theelements disposed within the pixel 12. The reduction in the number ofthe elements constituting the pixel 12 is important to improve the openarea ratio of the display panel 50. In detail, the drains of theP-channel MOS transistor 22 and the drive transistor 23 are directlyconnected to the current output 9 c of the current hold circuit 9. Thisresults in that the drain of the N-channel MOS transistor 28 is directlyconnected to the drain of the drive transistor 23.

The removal of the N-channel MOS transistor 25 requires preventing acurrent from flowing through the organic EL element 3 during programmingthe current hold circuit 9 with the constant current I₄ through theconstant current line 4. In order to preventing the current from flowingthrough the organic EL element 3, as shown in FIG. 20, the potential ofthe data signal inputted to the potential hold circuit 10 through thedata line 6 and the potential on the data-line control line 7 are bothselected so as to turn off the N-channel MOS transistor 28 while thecurrent hold circuit 9 is programmed with the constant current I₄. Inother words, the data signal and the data-line control line 7 are bothmaintained at the low level during programming the current hold circuit9 with the constant current I₄. This prevents a current from flowingthrough the organic EL element 3 while the current hold circuit 9 isprogrammed with the constant current I₄ through the constant currentline 4.

Seventh Embodiment

FIG. 21 shows the configuration of the pixel 12 in a seventh embodiment.The configuration of the pixel 12 in the seventh embodiment is almostidentical to the configuration shown in FIG. 19, in exception that theN-channel MOS transistors 26, 28 are replaced with the P-channel MOStransistors 26′, 28′. Since the N-channel MOS transistor 25 is removed,and the N-channel MOS transistors 26, 28 are further replaced with theP-channel MOS transistors 26′, 28′, the TFTs contained in the pixel 12have the same conductivity type. This reduces the number of the stepsrequired to fabricate the TFTs within the display panel 50, and isadvantageous in terms of the yield and cost.

In association with the fact that the N-channel MOS transistors 26, 28are replaced with the P-channel MOS transistors 26′, 28′, as shown inFIG. 22, the data signal transmitted through the data line 6, and thedata-line control line 7 are modified to be low active. That is, thepolarities of the data signal transmitted through the data line 6 andthe signal generated on the data-line control line 7 are inverted. Thisprevents a current from flowing through the organic EL element 3 duringprogramming the current hold circuit 9 with the constant current I₄ fromthe constant current line 4.

Eighth Embodiment

FIG. 23 shows the configuration of the display device in an eighthembodiment. In the eighth embodiment, M sub constant current controllines 30 are additionally disposed within the display panel 50, and thepixels 12 are further replaced with pixels 12′. If necessary, the subconstant current control lines 30 and the pixels 12′ may bedistinguished from each other with a subscript.

The potentials complementary to those on the constant current controllines 5 are developed on the sub constant current control lines 30. Asdescribed later, the sub constant current control lines 30 are used toprevent a current from flowing through the organic EL elements 3 duringprogramming the current hold circuits 9 with the constant currents I₄.

FIG. 24 shows the configuration of the pixel 12′. The structure of thepixel 12′ is almost identical to the pixel 12 in the first embodiment,in exception that the current hold circuit 9, the potential hold circuit10, and the switch 11 are replaced with a current hold circuit 9′, apotential hold circuit 10′, and a switch 11′, and that the sub constantcurrent control line 30 is connected to control input 9 c′ of thecurrent hold circuit 9′ in place of the constant current control line 5.

FIG. 25 shows the detailed configuration of the pixel 12′. The followingis a description on the difference between the pixel 12 in the firstembodiment and the pixel 12′. The N-channel MOS transistors 25, 26 and28 are replaced with the P-channel MOS transistors 25′, 26′ and 28′, andthe sub constant current control line 30 is connected to a gate of theP-channel MOS transistor 25′.

The aforementioned configuration of the pixel 12′ has an advantage thatall the TFTs within the pixel 12′ have the same conductivity type. Asmentioned above, the fact that all the TFTs have the same conductivitytype reduces the number of the steps required to form the TFTs in thedisplay panel 50, and this is advantageous in terms of the yield andcost. The use of the sub constant current control line 30, which arecomplementary to the constant current control line 5, is important forallowing all the TFTs contained in the pixel 12′ to have the sameconductivity type. The use of the sub constant current control line 30,complementary to the constant current control line 5, enables theP-channel MOS transistor 25′ to be used in place of the N-channel MOStransistor 25.

FIG. 26 is a timing chart showing operations of the display device inthe eighth embodiment. The operation of the display device in the eighthembodiment is equal to the operation of the display device in the firstembodiment shown in FIG. 6, except for that the P-channel MOS transistor25′ is operated in response to the sub constant current control line 30having the potential complementary to the potential of the constantcurrent control line 5, and that the potentials of the data-line controlline 7 and the data signal supplied to the pixel 12′ from the data line6 are complementary to those in the first embodiment.

Ninth Embodiment

In a ninth embodiment, operations of the display device is modified asshown in FIG. 27 in order to suppress the influence of discharge of thecapacitor element 24 within the current hold circuit 9′ in the eighthembodiment. The configuration of the display device in the ninthembodiment is equal to that in the eighth embodiment.

In the ninth embodiment, as shown in FIG. 27, in order to maintain thevoltage of the capacitor element 24, the current hold circuit 9 isprogrammed with the constant current I₄ multiple times for one frameperiod. The constant current control line 5 is activated when the datasignal is written through the data line 6 onto the potential holdcircuit 10, namely, while the data-line control line 7 is activated, andthereby the current hold circuit 9 is programmed with the constantcurrent I₄. Simultaneously with the activation of the constant currentcontrol line 5, the potential complementary to the constant currentcontrol line 5 is generated on the sub constant current control line 30,and thereby the P-channel MOS transistor 25′ is turned off. Thisprevents a current from flowing through the organic EL element 3.

In the ninth embodiment, the programming of the current hold circuit 9with the constant current I₄, namely, the charging of the capacitorelement 24 is repeatedly executed, and thereby the decrease in thevoltage across the capacitor element 24 is suppressed during theconstant current hold period. This decreases the difference between theconstant current I₄ and the drive current I₉, and improves the accuracyin the graylevel of the pixel 12.

Although the schema of the present invention and the preferableembodiments thereof have been described above, it should be noted thatthe variation are allowed within the scope of the invention disclosed inthe claims. In particular, it is apparent to those skilled in the artthat other current-driven elements may be used in place of the organicEL elements 3.

1. A display panel comprising: a current-driven display element; aconstant current control line; a constant current line providingconstant current continuously; a current hold circuit outputting, whensaid constant current control line is deactivated, a drive currenthaving an intensity substantially identical to that of a constantcurrent provided thereto through said constant current line in the casethat said constant current control line is activated; a switch circuitconnected between said current-driven display element and said currenthold circuit; a data line transmitting a data signal having a waveformcorresponding to a grayscale level; a control circuit provided with saiddata signal, wherein said control circuit turns on and off said switchcircuit in response to said data signal.
 2. The display panel accordingto claim 1, wherein transistors contained within said current holdcircuit, said switch circuit, and said control circuit are all TFTs. 3.The display panel according to claim 1, further comprising: anadditional switch circuit connected between said constant current lineand said current hold circuit, wherein said current hold circuit isconnected to a power supply terminal, and wherein said additional switchcircuit electrically connects said constant current line with saidcurrent hold circuit, and thereby allows said constant current to flowfrom said power supply terminal to said constant current line throughsaid current hold circuit.
 4. The display panel according to claim 3,wherein all MOS transistors contained within said current hold circuit,said switch circuit, said additional switch circuit, and said controlcircuit have the same conductivity type.
 5. The display panel accordingto claim 3, wherein said additional switch circuit includes a first MOStransistor, and wherein said first MOS transistor has a firstsource/drain connected to said constant current line, a secondsource/drain connected to said current hold circuit, and a gateconnected to said constant current control line.
 6. The display panelaccording to claim 3, wherein said current hold circuit includes a driveMOS transistor, a first capacitor element, a second MOS transistor,wherein said drive MOS transistor has a source connected to a powersupply terminal, a drain connected to said switch circuit and saidadditional switch circuit, wherein said first capacitor element isconnected between a gate and source of said drive MOS transistor, andwherein a source and a drain of said second MOS transistor are connectedto said gate and drain of said drive MOS transistor, respectively, whilea gate of said second MOS transistor is connected to said constantcurrent control line.
 7. The display panel according to claim 6, whereinsaid constant current flows from said power supply terminal to saidconstant current line through said drive MOS transistor, and saidadditional switch circuit, and thereby said first capacitor element ischarged to a source-to-gate voltage of said drive MOS transistor, andwherein said constant current is supplied for said current hold circuitmultiple times for one frame period.
 8. The display panel according toclaim 7, wherein said constant current is supplied for said current holdcircuit every time said data signal is provided for said controlcircuit.
 9. The display panel according to claim 6, wherein said currenthold circuit additionally includes a third MOS transistor, and whereinsaid third MOS transistor has a first source/drain connected to saiddrain of said drive MOS transistor, wherein a first source/drain of saidthird MOS transistor is connected to said switch circuit, and whereinsaid third MOS transistor has a gate connected to said constant currentcontrol line.
 10. The display panel according to claim 6, furthercomprising a sub constant current control line having a potentialcomplementary to a potential on said constant current control line,wherein said current hold circuit additionally includes a third MOStransistor, and wherein said third MOS transistor has a firstsource/drain connected to said drain of said drive MOS transistor, asecond source/drain connected to said switch circuit, and a gateconnected to said sub constant current control line, and whereinconductivity types of said first MOS transistor, said second MOStransistor, and said third MOS transistor are same.
 11. The displaypanel according to claim 1, further comprising a data-line control line,wherein said control circuit includes a potential hold circuitoutputting a potential substantially identical to a potential of saiddata signal from a signal output when said data line control line isactivated, and holding a potential on said signal output when said dataline control line is deactivated, and wherein said switch circuit isturned on and off, in response to said potential on said signal outputof said potential hold circuit.
 12. The display panel according to claim11, wherein said switch circuit includes a fourth MOS transistor,wherein said fourth MOS transistor has a first source/drain connected tosaid current hold circuit, and a second source/drain connected to saidcurrent-driven display element, wherein said potential hold circuitincludes: a fifth MOS transistor, and a second capacitor element,wherein said fifth MOS transistor has a first source/drain connected tosaid data line, a second source/drain connected to said signal output,and a gate connected to said data-line control line, and wherein saidsecond capacitor element is connected between a power supply terminaland said signal output.
 13. The display panel according to claim 1,further comprising a dummy circuit connected to said constant currentline, wherein said dummy circuit is provided with said constant currentthrough said constant current line during an inactive period while saidconstant current control line is deactivated.
 14. The display panelaccording to claim 13, further comprising a dummy constant currentcontrol line which is activated during an inactive period while saidconstant current control line is deactivated, wherein said dummy currentincludes: a drive transistor, a first MOS transistor, and a second MOStransistor, wherein said first MOS transistor has a first source/drainconnected to said constant current line, and a gate connected to saiddummy constant current control line, wherein said drive MOS transistorhas a source connected to a power supply terminal, and a drain connectedto a second/source drain of said first MOS transistor, and wherein saidsecond MOS transistor has a source and a drain connected to a gate andsaid drain connected to said drive MOS transistor, respectively, and agate connected to said dummy constant current control line.
 15. Thedisplay panel according to claim 1, further comprising a dummy pixelconnected to said constant current line, wherein said dummy pixel isprovided with said constant current through said constant current lineduring a predetermined period immediately before said constant currentcontrol line is activated, out of an inactive period while said constantcurrent control line is deactivated.
 16. The display panel according toclaim 14, wherein said predetermined period is longer than a timeconstant of charging a parasitic capacitor of said constant currentline.
 17. The display panel according to claim 1, wherein saidcurrent-driven display element is an organic EL element.
 18. A drivingmethod for a display panel including: a current-driven display element,a drive MOS transistor, a capacitor element connected between a gate anda source of said drive MOS transistor, a first switch connected betweena drain and said gate of said drive MOS transistor, and a second switchconnected between said drain of said drive MOS transistor and thecurrent-driven display element, said method comprising: a first step ofdeveloping a constant current through said drive MOS transistor withsaid first switch turned on and with said second switch turned off, asecond step of providing a drive current for said current-driven displayelement with said first switch turned off and with said second switchturned on.
 19. The driving method according to claim 18, wherein saiddisplay panel further includes a constant current line, and wherein saidconstant current is provided for said drive MOS transistor through saidconstant current line.
 20. The driving method according to claim 18,wherein said first step is performed multiple times for one frameperiod.